Field of the Invention
The invention relates to a flip-flop circuit, and particularly relates to a flip-flop circuit capable of decreasing a setup time.
Description of Related Art
In a design of a digital integrated circuit (IC), a flip-flop circuit is a commonly used register. In a chip level design, a scanning type flip-flop is usually applied in the design of a clock tree. In an application requiring a high-speed computation (for example, a high-speed central processing unit), in order to make the flip-flop circuit to satisfy the demand of the high-speed computation, to effectively decrease a setup time of the flip-flop circuit becomes an important demand.
In the conventional technical field, the flip-flop circuit may receive a data signal, and implement a data latch operation through a plurality of transmission gates. Generally, the flip-flop includes two latches connected in series, and the transmission gates in the latches may implement the data latch operation through complementary turning on or off operations. On the other hand, in order to decrease the setup time of the flip-flop circuit, in the conventional technique, a phase difference between a clock signal and an inverted clock signal in the flip-flop circuit can be adjusted for implementation. However, such method prolongs a CK to Q delay of a clock terminal to an output terminal of the flip-flop circuit.